The present invention relates to semiconductors.
A read only memory xe2x80x9cROMxe2x80x9d) is a device having a plurality of memory cells that permanently store bits of data. A resistive ROM typically includes a planar array of parallel word lines, which is perpendicular to and insulated from a planar array of parallel bit lines. A designated number of the memory cells in the ROM have a resistive, element connecting a node of one word line with a node of one bit line. The presence or absence of a resistive element in each memory cell determines whether a binary xe2x80x9c0xe2x80x9d or xe2x80x9c1,xe2x80x9d for example, is stored therein. The values stored within the ROM are xe2x80x9creadxe2x80x9d (i.e., output) by measuring a sense current flowing through each bit line from the memory cells of successive word lines.
Various ROM structures are known in the art. One known structure, referred to as a mask-written ROM, employs a semiconductor lithographic mask to xe2x80x9cwritexe2x80x9d (i.e., program) the values of the data bits into the memory cells of the ROM. The mask comprises a pattern for designating each memory cell in which the resistive element is to be fabricated.
With the desired storage capacity (i.e., the number of stored bits per device) of ROMs ever increasing, it follows that the number of cells needed has also been increasing. However, as the number of memory cells increase, the problem of crosstalk has grown. Crosstalk may be characterized as the misinterpretation of the value of bits in adjacent cells being the value of bits stored in cells to be read. Crosstalk results from the influence of the inevitable wire resistance in each bit line. As the number of cells increase, the wire resistance of each bit line increases relative to the resistance of each memory cell. Consequently, an increase in the wire resistance of each bit line increases the likelihood that a substantial portion of the sense current on one word line will be redirected onto an adjacent word line. This may cause the false reading of the binary values stored within each cell of the ROM.
One known approach for minimizing crosstalk has been to incorporate a supplemental resistancexe2x80x94e.g., a field effect transistorxe2x80x94in each memory cell of the ROM. The effective resistance of each cell may therefore be sufficiently increased relative to the wire resistance to reduce the likelihood that substantial amounts of sense current on one word line will be redirected onto an adjacent word line.
As industry drives towards increasing the density (i.e., the number of bits per unit area) of ROMs, however, the use of a field effect transistor as a supplemental resistance has become a problem. Field effect transistors require considerable unit area relative to each ROM cell. Consequently, an alternate ROM structure is needed having a sufficiently high relative memory cell resistance to minimize crosstalk and increase ROM density.
I have invented a memory structure, such as a ROM, that engenders maximum In density. In my invention, a resistance-altering constituent is disposed within at least one designated memory cell of a plurality of memory cells. More particularly, the resistance-altering constituent may be disposed within a conductive material forming each memory cell of the plurality. Consequently, a first numerical value may be interpreted as being stored in each designated cell and at least a second numerical value may be interpreted as stored in each remaining (non-designated) cell of the plurality. Advantageously, each designated memory cell has a first resistance, while each remaining memory cell has at least a second resistance. I have recognized that disposing the resistance-altering constituent within each designated memory cell sufficiently increases the information storage capability over presently available ROM structures.
In an illustrative example of my invention, each memory cell of the plurality is formed from a conductive layer, such as polycrystalline silicon. Furthermore, hydrogenxe2x80x94a Group 1A element of the Periodic Tablexe2x80x94is disposed within the conductive layer of each designated memory cell.
A memory structure embodying the principles of my invention may be advantageously fabricated using the techniques described in my co-pending, commonly assigned, U.S. Patent application, entitled xe2x80x9cA METHOD OF VARYING THE RESISTANCE OF A CONDUCTIVE LAYER,xe2x80x9d Ser. No. 09/888,879, filed concurrently with the present application on Jun. 25, 2001.